DRAMS and many other integrated circuits require a negative NMOS substrate voltage. A negative NMOS substrate voltage lowers the junction capacitance of NMOS transistors, prevents forward biasing of p-n junctions and improves the isolation of DRAM storage cells by increasing the threshold voltage of the thickfield transistors.
A negative substrate bias is achieved by using a capacitor to pump the substrate negative through a MOS diode. A typical substrate pump can be seen in FIG. 1. .PHI.1 and .PHI.2 are 180.degree. out of phase clock signals that oscillate between Vdd and Vss. When 01 is at Vdd, (D2 is at Vss and node N1 is precharged to Vss through PMOS transistor T1. When 4)1 goes from Vdd to Vss node N1 is booted to a negative potential and its charge is transferred to the substrate through PMOS diode D1. Node N1 going negative precharges node N2 to Vss through PMOS transistor T2. Thus we have a two phase substrate biasing pump. The substrate voltage is limited to -Vdd+.vertline.Vtd.vertline., where .vertline.Vtp.vertline. is the threshold voltage of the PMOS diode. It can be seen that the substrate voltage is dependent upon the voltage supply Vdd.
A problem may develop when Vdd slews from a higher voltage to a lower voltage and the substrate has no discharge path to enable it to become less negatively biased. When this happens, the threshold voltages of the integrated circuits NMOS transistors are too large for optimal operation of the circuitry, due to the body effect on the threshold voltages. A circuit, when in FIGS. 2, connected to the substrate pump of FIG. 1 overcomes this problem by causing the substrate voltage to become more shallow (less negative) during slew conditions.
In the circuit of FIG. 2, input N1 is connected to node N1 of the substrate pump of FIG. 1. Input N2 is connected to node N2 of the substrate pump of FIG. 1. The circuit of FIG. 2 operates by comparing the negative voltage of input N1 to node N3. When the voltage on input N1 is a high voltage, the voltage on input N2 is a low voltage so NMOS transistor T3 is off and the voltage on node N3 remains the same. When the voltage on input N1 is low, the voltage on input N2 is high so input N1's low voltage is then passed to node N3. Therefore, if input N1's low voltage becomes an NMOS threshold voltage (Vtn) above Vbb (substrate voltage), NMOS transistor T4 turns on and Vbb becomes more shallow until node N1's low voltage is .ltoreq.Vbb+Vtn. Since Vbb.gtoreq.-Vdd+.vertline.Vtp.vertline., Vdd must slew down by at least .vertline.Vtp.vertline.+Vtn for this circuit to be effective.
A major problem with circuits that have nodes at negative voltages is the risk of forward biasing the pn junctions in the NMOS transistors. If the drain or source of an NMOS transistor, shown in FIG. 3, gets a Vtpn (the turn on voltage of a pn junction diode) below Vbb, the diode becomes conductive and electrons are injected from the more heavily doped n-type source/drain area into the more lightly doped p-type substrate. Electrons injected into the more lightly doped p-type substrate travel freely until they either recombine in the substrate or are collected by a more positively charged region such as a DRAM storage cell. These injected electrons can cause DRAM storage cells to lose a true "1" stored in them if the number of injected electrons collected by a storage cell is large enough.
Input N1 in FIG. 2 is one such problematic injection node. The node voltage oscillates between ground and Vbb-.vertline.Vtd.vertline. causing the p-n diode from the source to the substrate of transistor T3 to become forward biased since Vbb is typically no deeper than (-Vdd)+.vertline.Vtp.vertline.. This result is undesirable. What is needed is a circuit that performs this same slew function without the risk of electron injection.